There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The FIG. 1 circuit 100 exemplary pixel cell 150 is a 3T APS, where the 3T is commonly used in the art to designate use of three transistors to operate the pixel. A 3T pixel has a photodiode 162, a reset transistor 184, a source follower transistor 186, and a row select transistor 188. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, and that in practical use there will be an M times N array of identical pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 converts incident photons to electrons which collect at node A. A source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particular row containing cell 150 is selected by a row selection transistor 188, the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 184 to node A. The gate of reset transistor 184 is coupled to a reset control line 191 which serves to control the reset operation in which Vrst is connected to node A. Vrst may be Vdd. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source following transistor 186 and its output is selectively coupled to a column line 170 through row select transistor 188. Although not shown in FIG. 1, column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor 188 is coupled to row select control line 160.
As know in the art, a value is read from pixel 150 in a two step process. During a charge integration period the photodiode 162 converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor 186 and selectively passed to column line 170 by row access transistor 188. During a reset period, node A is reset by turning on reset transistor 184 and the reset voltage is applied to node A and read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array of pixels 230 and a controller 232 which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 (FIG. 1) to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 3 more clearly shows the rows and columns 349 of pixels 350. Each column includes multiple rows of pixels 350. Signals from the pixels 350 in a particular column can be read out to a readout circuit 351 associated with that column. The read out circuit 351 includes sample and hold circuitry for acquiring the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits 351 then can be read sequentially column-by-column to an output stage 354 which is common to the entire array of pixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals are each supplied to the analog-to-digital converter.
FIG. 4 more clearly shows the column readout circuit 351 that includes a sample and hold read out circuit 401 and an amplifier 434. The FIG. 4 circuit is capable of sampling and holding and then amplifying the Vsig and Vrst values for subsequent use by an output stage 354 (FIG. 3).
For example, a Vsig from a desired pixel (“Vsig1”) coupled to column line 402 is stored on C1 capacitor 418 and a Vrst from the desired pixel (“Vrst1”) is stored on capacitor 420. Then the Vsig1 stored on C1 capacitor 418 is transferred and amplified by amplifier 434 to capacitor 462. Then Vrst1 is transferred and amplified by amplifier 434 to capacitor 460, at which point the Vrst and Vsig signals for the desired pixel are readout to an output stage 354. (FIG. 3).
As seen in FIG. 4, a first column line 402 is switchably coupled through SH1 switch 410 to the front side of C1 capacitor 418. The backside of C1 capacitor 418 is coupled to ground. The front side of C1 capacitor 418 is also switchably coupled through SH3 switch 414 through a buffer 430 to the front side of capacitor 438. The backside of capacitor 438 is coupled to a first input line to an amplifier 434. Vref is coupled to the second input line to amplifier 434. The first input line to the amplifier 434 is switchably coupled through Amp Rst switch 436 to the output of amplifier 434. The first input line to the amplifier 434 is also coupled through Amp Rst switch 436 to the output of amplifier 434. The output of amplifier 434 is switchably coupled through SHR1 switch 472 to a frontside of capacitor 460. The backside of capacitor 460 is coupled to ground. The frontside of capacitor 460 is switchably coupled through SHR2 switch 476 to a first input to output stage 354. The output of amplifier 434 is also switchably coupled through SHS1 switch 474 to a frontside of capacitor 462. The backside of capacitor 462 is coupled to ground. The frontside of capacitor 462 is switchably coupled through SHR2 switch 478 to a second input to output stage 354.
The operation of the FIG. 4 circuit is now described with reference to the simplified signal timing diagram of FIG. 5 (assuming a readout from a 3T pixel). To store Vsig1 on C1 capacitor 418 while the pixel is in the signal sampling phase, a pulse signal SH1 is applied which temporarily closes the SH1 switch 410 and couples the desired pixel with the front side of capacitor 418 through the column line 402. Thus, Vsig1 is stored on C1 capacitor 418. After the desired pixel is pulsed by a pixel reset signal, the pixel is in reset signal sampling phase. To store Vrst1 on capacitor 420 pulse signal SH2 is applied which temporarily closes the SH2 switch 412 and couples the desired pixel with the front side of capacitor 420 through the column line 402. Thus, Vrst1 is stored on C2 capacitor 420.
To transfer Vsig1 through the amplifier 434, pulse signals Amp Rst, SH3, and SHS1 are applied which temporarily closes SH3, Amp Rst, and SHS1 switches 414, 436, and 474 and forces the signal stored on the front side of capacitor 418 and carried on line 402 through amplifier 434 after going through a buffer 430 and a capacitor 438. The signal output from amplifier 434 is stored on capacitor 462. Thus, the amplified Vsig1 signal is stored on capacitor 462.
To transfer Vrst1 through the amplifier 434, pulse signals SH4 and SHR1 are applied which temporarily closes SH4 and SHR1 switches 416 and 472 and forces the signal stored on the front side of capacitor 420 and carried on line 402 through amplifier 434 after going through a buffer 430 and a capacitor 438. The signal output from amplifier 434 is stored on capacitor 460. Thus, the amplified Vrst1 signal is stored on capacitor 460. Vsig1 and Vrst1 signals are transferred to output stage 354 by applying pulses SHR2, SHS2 enabling and closing respective SHR2, SHS2 switches 476, 478.
In pixels arrays, where real estate is precious it would be desirable to shared the column readout circuitry among a plurality of column lines.